library ieee;
use ieee.std_logic_1164.all;

entity frequencies is
    port(clk: in std_logic;
         q: buffer std_logic);
end frequencies;

architecture behave of frequencies is
begin
    process(clk)
        variable time: integer range 0 to 12500000;
    begin
        if rising_edge(clk) then
            time := time + 1;
            
            if time = 12500000 then
                q <= not q;
                time := 0;
            end if;
        end if;
    end process;
end behave;
